The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly, to vertical channel semiconductor devices and methods of manufacturing the same.
As the integration density of semiconductor devices increases, the size of features, such as metal oxide semiconductor (MOS) transistors (i.e., the channel length of a MOS transistor) decreases so that more devices may be integrated on a substrate in a given area. However, when the channel length of the MOS transistor decreases, short channel effects (e.g., a drain induced barred barrier lowering (DIBL) effect, a hot carrier effect and/or a punch trough effect) may also be caused, which may affect performance of the high integration density semiconductor device. Various methods have been proposed to address short channel effects. One method is to reduce the depth of a junction region and another method is to form a groove in a channel region to relatively extend the channel length.
However, in the case of a semiconductor memory device, such as a dynamic random access memory (DRAM), a MOS transistor with a channel length of below an exposure limit is generally required as the integration density approaches a gigabit level. Therefore, a planar type MOS transistor, in which a source and a drain are formed on substantially the same plane, is difficult to implement in a gigabit memory device.
Vertical channel semiconductor devices have been proposed in which a source and a drain are vertically arranged to form a vertical channel. FIG. 1 is a cross-sectional view of a conventional vertical channel semiconductor device. As shown in FIG. 1, the vertical channel semiconductor device includes pillars 15 that may be defined in a semiconductor substrate 10 by a hard mask pattern. A gate electrode 25 is shown formed on the surface of the pillar 15 that surrounds the periphery of the pillar 15. A gate insulation layer 20 is interposed between the gate electrode 25 and the pillar 15. A drain region 30a is formed in the substrate 10 between the pillars 15, and a source region 30b is formed on the upper surface of the pillar 15 between (surrounded by) the gate electrodes 25. A bit line 35 is selectively formed on the surface of the drain region 30a. An interlayer insulating layer 40 is formed between the pillars 15 so as to insulate the pillars 15 from each other, and a contact pad 45 is formed to contact with the source region 30b. An insulating layer 50 is formed between the source contact pad 45 and the interlayer insulating layer 40 so as to insulate the source contact pad 45 and the interlayer insulating layer 40 from each other.
A channel between the source region 30b and the drain region 30b is formed with a substantially vertical type architecture as the source region 30b is formed in the upper region of the pillar 115 and the drain region 30a is formed in the lower region of the pillar 15. Therefore, the channel length may not be affected by a decrease in the planar surface area of the MOS transistor.
Thus, while the planar area required for a MOS transistor may be decreased with a vertical architecture, the channel length may not be affected as the planar area of the vertical channel semiconductor device, including the areas of the pillar 15 and the source region 30b, decrease. However, the area of the contact pad 45 contacting with the source region 30b decreases, which may increase the contact resistance. As the insulating spacer 50 is formed over the pillar 15 to insulate the contact pad 45 from the gate electrode 25, the area of the contact pad 45 further decreases due to the area occupied by the insulating spacer 50, which may even further increase the contact resistance to the source region 30b. This structure may also increase the contact resistance of a storage electrode that will contact with the contact pad 45.
Moreover, the bit line 35 is typically formed by exposing a predetermined portion of the drain region 30a and selectively forming a conductive layer in the exposed drain region 30a. As such, the exposed drain region 30a is also narrowed with increasingly high integration density of the semiconductor device and the contact area between the drain region 30a and the bit line 35 is also narrowed, which may make it difficult to obtain a low contact resistance between the drain region 30a and the bit line 35.